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Officials last week revealed that the U.S. contribution to ITER could cost $3.9 billion by 2034—roughly four times the...
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Three years ago, Jennifer Francis of Rutgers University proposed that a warming Arctic was altering the behavior of the...
- 17 April 2014 12:48 pm , Vol. 344 , #6181
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Teeny Tiny Transistor
17 October 1997 8:00 pm
TOKYO--Circuit designers at NEC Corp. have probed what some thought was a lower limit on the size of microelectronics--and found some give. By combining a novel design with high-precision techniques for carving semiconductors, the NEC team has developed an experimental transistor with a key feature that's 20 times smaller than in the transistors found on the densest commercially available chips.
"Nobody has yet reported work at such small dimensions," says Sandip Tiwari, a small-device researcher at IBM's T. J. Watson Research Center in Yorktown Heights, New York. The device, announced at a recent conference in Japan, is mainly a proof of principle, however, since its design isn't suited to being packed in large numbers on a chip.
The NEC group, led by Hisao Kawaura, varied a standard transistor design in which a central semiconducting channel lies between source and drain electrodes, created by "doping" the base material with impurities that carry an excess of electrons. Above the central channel is a third electrode, called the gate. The gate turns the transistor on or off by controlling the conductivity of the channel, either allowing electrons to flow from source to drain or cutting off the current, and there is a lower limit on its size. Too small, and electrons will manage to sneak through even when the device is off. Some researchers had put this lower limit at 30 nanometers (billionths of a meter).
But the NEC team was able to build a working transistor with a gate half that size by adding a second gate, shaped something like a top hat with the crown above the first gate and brims above both sides of the channel. This second gate allowed the researchers to leave insulating gaps between the channel and the doped source and drain regions. To create a route for current, a voltage applied to the upper gate attracts electrons to the surface of the base material, forming conductive, ultrashallow source and drain regions. These electrically induced regions are far shallower than anything that can be formed with present doping techniques; and the shallower source and drain confine the current so that a narrower gate can control it.